1. Field of the Invention
This invention relates to a phase locked loop, and in particular to a digital phase locked loop capable of recovering a clock signal from one or more input signals subject to jitter.
2. Description of the Prior Art
In digital networking applications, there is a requirement to provide timing references to interface circuits to T1 and E1 (see EPT) primary rate digital transmission links. These timing signals must meet ACCUNET R T1.5 and ETS1 ETS 300 01111 specifications for a 1.544 MHz (T1) or 2.048 MHz (CEPT) input reference. These specifications impose strict requirements on jitter and stability.
The common method of providing such timing signals is to use a phase locked loop. Typically, this consists of a phase detector comparing the input signals with the output of the loop divided by a suitable factor, a loop filter to eliminate high frequency fluctuations, and a controlled oscillator whose frequency is controlled in such a way as to eliminate the phase difference detected by the phase detector.
It has long been known to employ a VCO (voltage controlled oscillator) as the controlled oscillator in the loop. U.S. Pat. No. 4,577,163 discloses a phase locked loop in which the VCO is replaced by a DCO (digital controlled oscillator) whose output is divided by a factor K and fed back to the phase detector. In the patent, the DCO is clocked by a clock signal F.sub.clock. Since the DCO cannot respond to phase shifts less than one clock cycle, F.sub.clk is the limiting factor for accuracy in this type of phase locked loop. In order to meet ACCUNET specs, a local oscillator having a frequency of 200 MHz or more must be employed.
Such high frequency local oscillators are expensive, energy-consuming, and prone to the emission of electromagnetic interference (EMI).
U.S. Pat. No. 5,218,314 discloses a phase locked loop in which a local oscillator feeds a tapped delay line. The output signal is taken from one of the taps of the delay line according to a phase comparison effected with the input signal. The problem with this arrangement is that it provides no jitter suppression for the reference signals. As a practical matter, due to the inherent properties of the transmission medium, incoming T1 and E1 signals will be subject to jitter, and this must be substantially suppressed in order to meet the ACCUNET specifications.
An object of the invention is to provide a phase locked loop that alleviates the aforementioned problems with the prior art.